The present invention relates to integrated circuits and to methods of manufacturing integrated circuits. More particularly, the present invention relates to a method of reducing integrated circuit contact size using spacer filling, thereby reducing charge-gain effects.
Integrated circuits (ICs), such as, ultra-large scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit can include complementary metal oxide semiconductor (CMOS) field effect transistors (FETS). ICs often include flash memory cells.
Flash memory cells are generally comprised of a transistor connected to a word line and a bit line. The transistor includes a gate stack comprised of a polysilicon cap, a control gate, a control gate dielectric, a floating gate and a tunnel oxide. The polysilicon cap is disposed over the control gate, which is disposed over the control gate dielectric. The control gate dielectric is disposed over the floating gate, which is disposed over the tunnel oxide. The gate stack is located between a source and a drain. An insulative spacer abuts each side of the gate stack. The drain is connected to the bit line through a contact. The word line is connected to the control gate of the transistor. The flash memory cell stores data (e.g., a 1 or 0) in the floating gate.
Generally, the transistor is covered by a high temperature oxide and an interlevel dielectric to insulate it from subsequently formed metal layers. An aperture or hole is etched through the interlayer dielectric and the high temperature oxide. The hole is filled with a conductive material to provide connections to the transistor, to conductors, or other circuit structures. For example, a contact can extend from the bit line through the interlevel dielectric to the drain of the transistor. In another example, a contact or conductive via can extend through the interlevel dielectric to connect to the gate stack.
As transistors disposed on integrated circuits (ICs) become smaller (e.g., transistors with gate lengths approaching 50 nm), CMOS fabrication processes must scale the dimensions of the transistors. That is, there must be proportional operational characteristics of structural elements in the ultra-small dimensions of a sophisticated transistor.
One problem associated with CMOS scaling involves spacing between gate stacks and contacts. As mentioned above, contacts are required in an IC device to provide electrical connections between layers or levels of the integrated circuit device. Semiconductor devices typically include a multitude of transistors which are coupled together in particular configurations through contacts.
Contacts are generally coupled to the source region and/or drain region of the transistors disposed on the integrated circuit. The contact is often connected to the source and drain region via a silicide layer formed in a high temperature process. The silicide layer reduces drain/source series resistance.
In conventional processes, contacts must be spaced from the gate conductor by a minimum acceptable distance (often at least one minimum lithographic feature). Charge loss and charge gain can occur when electrons travel laterally through the high temperature oxide or interlayer dielectric between the contact and the floating gate. Such charge gain and loss in the floating gate can destroy or corrupt the data stored in the memory cell.
Indeed, as integrated circuits have become more dense, distances between transistors and transistor components has become smaller. As the distance between contacts and floating gates decreases, a transistor""s susceptibility to charge gain and loss is also increased. Therefore, charge gain and loss problems associated with contacts can be particularly troublesome as integrated circuits contain more transistors.
One possible solution is to increase the space on the IC layout. Nevertheless, increased contact to gate structure spacing results in lower device density. Another possible solution is to reduce the contact size by printing smaller contacts. However, printing very small contacts is a challenge to lithography. Further, small contacts cause problems associated with high contact resistance.
Thus, there is a need to reduce the charge-gain problem associated with spacing between the contact and the gate structure. Further, there is a need to provide an integrated circuit with minimal contact to gate structure spacing while using contacts which do not have high contact resistance. Even further, there is a need to reduce contact size while avoiding manufacturing difficulties associated with small contacts.
One embodiment of the invention relates to a method of reducing contact size in an integrated circuit. The method includes providing an insulating layer over a semiconductor substrate including a plurality of gate structures, creating an aperture extending through the insulating layer and having side walls, providing a spacer on the side walls of the aperture, and providing a contact in the aperture. The lateral sides of the contact abut the spacer.
Another embodiment of the invention relates to a method of forming an electrical contact in an integrated circuit which includes a gate structure. The electrical contact is located at a distance from the gate structure which avoids charge gain between the contact and the gate structure. The method includes providing a contact hole having side walls and extending through an insulating layer covering the gate structure, providing a spacer material along the side walls of the contact hole, and filling the contact hole with an electrical contact material.
Another embodiment of the invention relates to an integrated circuit including a gate structure and an active region. The integrated circuit includes an insulating layer disposed over the gate structure and the active region, a contact traversing the insulating layer from the top of the layer to the active region, and an insulating spacer abutting the lateral sides of the contact.